1. Field of the Invention
The present invention relates to an imaging device chip set and an image pickup system for use in a digital camera, etc., and particularly to an imaging device chip set and an image pickup system in each of which a MOS-type imaging chip and a DSP chip are included.
2. Related Background Art
Recently, rapid-paced advances of the digital signal processing technology and the CMOS micromachining technology have made it possible to provide a one-chip CMOS camera in which a digital signal processor (DSP) capable of performing high-level signal processing operations and an imaging element that converts optical signals projected to an imaging surface into electric signals and takes out the same are integrated on one silicon substrate.
FIG. 7 is a view illustrating a configuration of a conventional one-chip CMOS camera 80. The one-chip CMOS camera 80 includes a sensor part 207 that converts light into electric signals. In a sensor part 207, a plurality of unit pixels 1 are arranged in matrix. The CMOS camera 80 includes a vertical scanning circuit 205, a horizontal scanning circuit 206, and a timing generating circuit 203 for driving the unit pixels 1 arranged in the sensor part 207. The CMOS camera 80 includes a gain control amplifier 204 for amplifying signal outputs from the unit pixels 1 arranged in the sensor part 207, an analog digital converting circuit 208 for converting output signals from the gain control amplifier 204 into digital signals, and a digital signal processing circuit 202 for performing digital signal processing with respect to digital signals obtained through the conversion by the analog-digital converting circuit 208.
While the one-chip configuration has been enabled by the CMOS micromachining technology that has advanced highly, it has been found that a two-chip configuration in which the imaging chip and the DSP chip are formed independently has advantages in performance and cost.
A DSP chip has a more sophisticated signal-processing function for carrying out high-level signal processing with respect to an enormous volume of image information. In the case of still images, it is necessary to compress the image information greatly so as to transmit images through portable telephones that will progress significantly from now on. More specifically, for this purpose, a compressing method called JPEG is available. To compress data by JPEG, it is necessary to perform an enormous amount of calculation at a high speed. Therefore, the CMOS micromachining technology and the latest CMOS circuit designing technology are indispensable. Further, in the case where motion pictures are handled ultra-high-speed processing circuits are required. Thus, a DSP chip necessarily uses the most advanced digital CMOS micromachining technology.
On the other hand, an imaging chip deals with analog signals. Further, the miniaturization of a photosensitive region arranged in an imaging chip cannot be promoted rapidly due to limitations relating to lenses used in cameras. Thus, the manufacturing processes required for the DSP chip and the imaging chip are different. If the chips are arranged on one chip by brute force combination, there is a possibility of deteriorating the performance of the imaging chip that is arranged in one chip together with the DSP, due to the higher speed of the DSP, the micromachining process used as the manufacturing process, and digital noises of the DSP. Therefore, the configuration in which the imaging chip and the DSP chip are arranged independently has an advantage.
FIG. 8 is a block diagram illustrating a configuration of another conventional imaging device chip set 90. The imaging device chip set 90 includes an imaging chip 210 and a DSP chip 211. The imaging device chip set 90 in which the imaging chip 210 and the DSP chip 211 are arranged independently is configured so that, irrespective of the signal processing method and the type of the DSP, a vertical scanning circuit 205 and a horizontal scanning circuit 206 for driving a sensor part 207, a timing pulse generating circuit 203 for generating pulses necessary for the vertical scanning circuit 205 and the horizontal scanning circuit 206, a gain control amplifier 204 for amplifying a signal output from the sensor part 207, and an analog-digital converting circuit 208 for converting an output signal from the gain control amplifier 204 to a digital signal are mounted on an imaging chip 210, so as to cause the imaging chip to operate independently. A digital signal processing circuit 98 is mourned on a DSP chip 211.
A reference pulse is supplied from the DSP chip 211 to the imaging chip 210 via a master clock line 212. Further, an electronic shutter signal is supplied from the DSP chip 211 to the imaging chip 210 via an electronic shutter signal line 213 for controlling sensitivity. From the imaging chip 210 to the DSP chip 211, a digital signal from the analog-digital converting circuit 205 is supplied to the digital signal processing circuit 98 via a signal line 214.
In the two-chip configuration that the above-described conventional technology proposes with a view to achieving the lower cost and the higher performance, the added value of the DSP chip relating to the performance and the cost are increased by employing the CMOS micromachining technology and incorporating the digital signal processing technology that has been advancing rapidly. However, for the imaging chip, a modest micromachining technology has to be used so as to ensure analog performance, and this increases the area of the digital circuits such as the timing pulse generating circuit 203, which inherently are formed with CMOS logics advantageously. Consequently, the two-chip configuration has not achieved any great advantage in the cost aspect, as compared with the one-chip configuration.
By mounting the timing pulse generation circuit 203, the gain control amplifier 204, and the analog-digital converting circuit 208 on the DSP chip 211, it is possible to attempt to reduce the cost. However, in this case, the number of lines for supplying timing pulses from the DSP chip 211 to the imaging chip 210 increases, and noises are superposed on the supply lines, whereby the noises are superposed on a noise output of the imaging chip 210. As a result, the sensitivity of the imaging chip 210 decreases, thereby leading to the degradation of the performance. It has been known that the noises are generated due to fluctuations of current supplied to the vertical scanning circuit 205 and the horizontal scanning circuit 206 for mainly driving the sensor part 207.
In the case where the vertical scanning circuit 205 and the horizontal scanning circuit 206 are formed with CMOS logics, the current fluctuations are caused by a so-called flow-through current that is generated upon the switching of the CMOS circuits. It is also known that generally, a CMOS circuit is characterized by small power consumption, but a great current (flow-through current) flows at the moment of switching of the CMOS circuit. This is because only at an instant upon the switching, both of n-MOS and p-MOS transistors are turned ON, which causes a short circuit between a power source and a ground. In the case where a line for controlling the switching is arranged outside the chip, noises are superposed on the line itself, or pulses passing through the line are dulled, thereby increasing noises of the power source due to the flow-through current. Therefore, the earlier possible establishment of the two-chip configuration system technology with which requirements of the lower cost and the higher performance are satisfied is being demanded.
An object of the present invention is to provide an imaging device chip set and an image pickup system in which both of the imaging chip and the DSP chip have an increased added value.